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The VCOMPLX pins should be left floating if the PLL is not being used. Refer to the Axcelerator
Family FPGAs and RTAX-S/L Family FPGAs datasheets for pin assignment information.
2. Since the AX and the RTAX-S/L devices are exactly pin compatible except for the PLL, which the
RTAX-S/L does not have, designing the PCB with VCCPL(X) pins connected to 1.5 V will not affect
the function of the RTAX-S/L devices. Pins for VCOMPL(X) can be designed with land patterns only.
These 16 PLL pins are not connected internally inside the RTAX-S/L packages.
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Visit Technical Support online at www.microsemi.com/soc/support/search/default.aspx
Email Technical Support at soc_tech@microsemi.com
Call Technical Support between 7:00 AM and 6:00 PM Pacific Time, Monday through Friday:
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Related Documents
Application Notes
Ceramic Column Grid Arrays (CCGA)
www.microsemi.com/soc/documents/CCGA_AN.pdf
Datasheets
Axcelerator Family FPGAs
www.microsemi.com/soc/documents/AX_DS.pdf
RTAX-S RadTolerant FPGAs
www.microsemi.com/soc/documents/RTAXS_DS.pdf
Pin Mapping Lists
All pin mapping lists are available at www.microsemi.com/soc/techdocs/package/default.aspx.
List of Changes
The following table lists critical changes that were made in each revision of the document.
Revision*
55900016-4/11.11
55900016-3/7.06
Changes
Added 2 lines at the end of "Introduction" section (SAR 33472).
All tables were updated to include current ordering part numbers
Clarifying notes added to Step 5 and Figure 12
Page
1
1, 10,
and 11
6, 9
Note: *The revision number is located in the part number after the hyphen. The part number is displayed at the bottom
of the last page of the document. The digits following the slash indicate the month and year of publication.
11
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